1. Field of the Invention
The present invention relates to a wiring pattern determination method for determining wiring patterns of plated leads in the vicinity of an edge of a semiconductor package having a multi-layered structure, as well as a computer program product for allowing a computer to perform this wiring pattern determination process.
2. Description of the Related Art
A semiconductor package, such as a PBGA or an EBGA, is designed so that electrode terminals of a semiconductor chip are electrically connected with pads (for example, wire bonding pads or flip-chip pads) and the pads are connected with vias (lands) and the vias are also connected with each other by wiring patterns. A designer can design wiring routes of a semiconductor package by trial and error on a virtual plane and using a CAD system but, at this time, this design work takes much time and effort.
In order to solve this problem, as set forth in Japanese Unexamined Patent Publication No. 2002-083006, there has been proposed a technique in which only wiring routes are determined in advance in a rough wiring process and, then, by referring to actual design rules and by checking lines and spaces, automatic wiring is performed uniformly in a wiring formation process.
On the edges of a semiconductor package, plated leads are wired from terminals to which respective wiring patterns are connected. FIG. 16 is a diagram illustrating plated leads located on an edge of a semiconductor package. In particular, in this figure, there are shown plated leads 11 on one of four edges 10 of a semiconductor package. The plated leads 11 have to be wired in a direction perpendicular to the edge 10 of the semiconductor package.
Such a plated lead wiring method that can easily perform automatic wiring of the plated leads is set forth in Japanese Unexamined Patent Publication No. 2002-149734, as an example.
In a manufacturing stage, a plurality of semiconductor packages are fabricated simultaneously on one large substrate. After the desired wiring patterns are formed, the one substrate, in which the plurality of semiconductor packages are fabricated, is divided into single semiconductor package so that the semiconductor packages are finished as final products.
Further, in recent years, there exists a semiconductor package having a multi-layered structure, in which wiring patterns are formed not only in one layer on a substrate but wiring patterns that are different from each other are formed in a plurality of layers for higher integration.
In the semiconductor package having such multi-layered structure, if plated lead positions on its edge are overlapped between successive layers in a lamination direction, thick and hard portions appear on the substrate and, as a result, when the substrate is divided into each semiconductor package, in a manufacturing stage, burrs may be formed at the divided portions and the plated leads or the substrate itself may be damaged. FIG. 17 is a cross-sectional view illustrating a cutting plane on an edge of a semiconductor package having a multi-layered structure in which plated lead positions are overlapped between successive layers. This figure shows a cross-section of a semiconductor package having a two-layered structure in which plated leads are overlapped in the lamination direction of two substrates 13-1 and 13-2.
In order to avoid the problem in the manufacturing stage of the semiconductor package having the multi-layered structure as described above, the plated lead positions should not overlap on the successive layers. FIG. 18 is a cross-sectional view illustrating a cutting plane on an edge of a semiconductor package having a multi-layered structure in which the plated lead positions are not overlapped between the successive layers. Similarly to FIG. 17, this figure shows a cross-section of a semiconductor package having a two-layered structure. As shown in the figure, the positions of the plated leads 11 are disposed alternately so that the plated lead positions do not overlap on the successive layers of the substrates 13-1 and 13-2 on the edge of the semiconductor package. As a result, when the substrate is divided into single semiconductor packages in the manufacturing stage, burrs are not formed on the divided portions and the cut surfaces can be finished properly.
Conventionally, positions of plated leads on an edge of a semiconductor package having a multi-layered structure are designed by trial and error, or by making and correcting the wiring actually while manipulating a CAD system manually, depending on the designer's experience and intuition. More specifically, first, based on already designed wiring patterns, the positions of the plated leads wired from terminals, to which respective wiring patterns are connected, are designed tentatively. Next, by using the CAD system, the tentatively designed plated lead positions are moved and corrected so that (1) requirements for clearance can be satisfied, (2) the plated lead positions are not overlapped between successive layers, and, further, (3) the resulting plated lead positions are not too different from the tentatively designed plated lead positions and, as a result, optimal plated lead positions are determined.
In such wiring design technique by trial and error, the design quality and the time required for design greatly depend on the designer's skill, experience, intuition and the like. In particular, as the number of layers in the multi-layered structure of the semiconductor package is increased, the effort, time and difficulty for achieving the optimal plated lead positions is increased. For example, even a correction of the plated lead positions in only one layer may affect the plated lead positions in other layers significantly and, therefore, the entire multi-layered structure may often have to be redesigned.
Further, in the case of the semiconductor package having the multi-layered structure, the number of variations of the plated lead positions that can be designed is far more than that in the case of the one-layered semiconductor package and, therefore, it is difficult to automate the design due to its complexity and, after all, such a semiconductor package has to be designed manually by trial and error. In reality, because the manual design by trial and error requires about half a day to three days and it is not economical to waste further time on wiring design, the designer has to compromise with a certain design quality.
In view of the above problems, it is an object of the present invention to provide, in a wiring pattern determination process for determining optimal wiring patterns of plated leads in the vicinity of an edge of a semiconductor package having a multi-layered structure, a wiring pattern determination method for facilitating its process, as well as a computer program product for allowing a computer to perform this wiring pattern determination process.